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Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesa LSIs
M6MGD967W33ATP
100,663,296-BIT (6,291,456-WORD BY 16-BIT) CMOS FLASH MEMORY 33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS Mobile RAM & Stacked- MCP (micro Multi Chip Package)
DESCRIPTION
The M6MGD967W33ATP is a Stacked micro Multi Chip Package (S- MCP) that contents 96M-bit Flash memory and 32M-bit Mobile RAM in a 52-pin TSOP. 96M-bit Flash memory is constructed by 64M-bit Flash Memory and 32M-bit Flash Memory. They are single power supply and high performance non-volatile memory. All memory blocks are locked and can not be programmed or erased, when F-WP# is Low. Using Software Lock Release function, program or erase operation can be executed. The M6MGD967W33ATP is suitable for a high performance cellular phone and a mobile PC that are required to be small mounting area, weight and small power dissipation.
FEATURES
Access time Flash Mobile RAM 85ns (Max.) 85ns (Max.)
32M-bit Mobile RAM is a 2,097,152 words high density Supply voltage FM-VCC = 2.7 ~ 3.0V RAM fabricated by CMOS technology for the peripheral Ambient temperature Ta=-40 ~ 85 C circuit and DRAM cell for the memory array. The interface is Package 52pin TSOP(Type-II), Lead pitch 0.4mm compatible to an asynchronous SRAM. The cells are automatically refreshed and the refresh control is not required for system. The device also has the partial block refresh scheme and the power down mode by writing the command.
APPLICATION
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
A15 A14 A13 A12 A11 A10 A9 A8 A19 M-CE # WE # F-RP# F-WP# NC NC A21 A20 A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
A16 F-CE2 # M-UB# GND M-LB# DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 FM-VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE # GND F-CE1# A0
10.79 mm
10.49 mm
FM-VCC GND A0-A20 A21 DQ0-DQ15 F-CE1# F-CE2# M-CE# :Common VCC for Flash / Mobile RAM :Common GND for Flash / Mobile RAM :Common address for Flash / Mobile RAM :Address for Flash :Data I/O :Flash chip enable1 for lower 32M-bit Flash :Flash chip enable2 for upper 64M-bit Flash :Mobile RAM chip enable OE# WE# F-WP# F-RP# M-LB# M-UB#
Outline 52PTF
:Output enable for Flash/Mobile RAM :Write enable for Flash/Mobile RAM :Write protect for Flash :Reset power down for Flash :Lower byte control for Mobile RAM :Upper byte control for Mobile RAM
1
Rev.1.0.48a_bbzb
Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesa LSIs
M6MGD967W33ATP
100,663,296-BIT (6,291,456-WORD BY 16-BIT) CMOS FLASH MEMORY 33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS Mobile RAM & Stacked- MCP (micro Multi Chip Package)
MCP Block Diagram
F-Vcc GND
A0 to A21 A0 to A21 F-CE2#*
64Mbit DINOR IV Flash Memory
DQ0 to DQ15 A0 to A20 WE# OE# F-WP# F-RP# F-CE1#*
32Mbit DINOR Flash Memory
S-Vcc
A0 to A20 32Mbit Mobile RAM
M-UB# M-LB# M-CE#
* ... F-CE1#="L" is valid for lower 32M-bit, F-CE2#="L" is valid for upper 64M-bit, respectively. It is noted that F-CE1#=F-CE2#="L" is forbidden mode.
Note: In this datasheet there are the expressions of "VCC" which means "FM-VCC". In Mobile RAM part there are the expressions of "UB#" and "LB#" which mean "M-UB#" and "M-LB#", respectively. In 32Mb Flash Memory part there are the expressions of "F-CE#" which means "F-CE1#". In 64Mb Flash Memory part there are the expressions of "F-CE#" which means "F-CE2#".
Capacitance
Symbol Parameter A21-A0, OE#, WE#, S-UB#, S-LB#, Input S-CE1#, S-CE2, F-CE1#, F-CE2#, Capacitance F-WP#, F-RP# Output Capacitance DQ15-DQ0 Test Condition Limits Typ. Unit
Min.
Max.
CIN
Ta=25C, f=1MHz, Vin=Vout=0V
26
pF
COUT
34
pF
2
Rev.1.0.48a_bbzb
Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGD967W33ATP
100,663,296-BIT (6,291,456-WORD BY 16-BIT) CMOS FLASH MEMORY 33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS Mobile RAM & Stacked- MCP (micro Multi Chip Package)
Nippon Bldg.,6-2,Otemachi 2-chome, Chiyoda-ku,Tokyo,100-0004 Japan
Keep safety first in your circuit designs!
* Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with app ropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* These materials are intended as a reference to assist our custom ers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. * Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials , and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product informati on before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com ). * When using any or all of the information contained in these mate rials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Renesas Technology Corporation semiconductors are not designed or manuf actured for use in a device or system that is used under circums tances in which human life is potentially at stake. Please conta ct Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese ex port control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a coun try other than the approved destination. * Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. * Please contact Renesas Technology Corporation for further details on these materials o r the products contained therein.
REJ03C0005 (c) 2003 Renesas Technology Corp. New publication, effective April 2003. Specifications subject to change without notice

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